A programmable logic device (PLD, e.g., a field programmable gate array (FPGA) or a complex programmable logic device (CPLD)) may be used in a variety of applications and may provide certain advantages over other types of devices. For example, a PLD offers the advantage of being reprogrammable in the field (e.g., a field update, with the PLD in its operational environment).
A drawback of a conventional PLD is that, while its configuration memory is being reprogrammed, the PLD typically cannot preserve data stored in its volatile memory (e.g., volatile embedded random access memory (RAM) blocks or registers) and, consequently, the data is lost during the reprogramming process (e.g., registers are reset with a global reset signal). However, depending upon the particular application, a user of the PLD may prefer to preserve the data stored in the volatile memory for use within the PLD after the reprogramming (e.g., reconfiguration) of the PLD has been completed and the PLD is operating based upon the new configuration data provided during the reprogramming (e.g., a user mode of operation).
A conventional approach to preserve the data stored in volatile memory during the reprogramming process, for example, is to read from the PLD the data that a user desires to preserve and merge this data with the new configuration data prior to the reprogramming process. However, this process is time consuming and complex and may be difficult to achieve for some types of applications.
As a result, there is a need for improved reprogramming techniques for PLDs.